An 8-bit 1-GHz SAR ADC with Charge-Sharing Sampling and Embedded Auto-Zero Comparator for Ultra-High-Speed Wireline Systems

Abstract

This paper presents an 8-bit 1-GHz single-channel successive approximation register (SAR) analog-to-digital converter (ADC) targeting ultra-high-speed wireline systems. The proposed design features a charge-sharing sampling technique with halved sampling time constant that accelerates quantization speed, and a novel embedded auto-zero comparator eliminating offset with minimal overhead. Fabricated in 28-nm CMOS technology and operating at 1-V supply, the ADC achieves 48.51-dB signal-to-noise-and-distortion ratio (SNDR) and 63.46-dB spurious-free dynamic range (SFDR) at a 1-GHz sampling rate while consuming 3.66 mW. Occupying only 0.0061 mm² core area, it demonstrates a figure-of-merit (FoMw) of 16.74 fJ/conv.-step(post-layout).