Analysis and Design for Type-II Double-Sampling Phase-Locked Loops
Keywords:
Double-sampling PLL (DSPLL),
phase-domain model,
voltage-domain model,
phase noise,
Verilog-A
Article ID: 22.20250597
Details
Article ID: 22.20250597
This letter presents a unified phase- and voltage-domain modeling framework for type-II double-sampling phase-locked loops (DSPLLs). An improved analytical phase-domain model is derived by refining the phase detector's transfer function. A Verilog-A based voltage-domain model is developed, enabling fast transient-only phase noise analysis. We clarify the noise contribution of the S/H clocks. We further extend the reference phase noise 3dB-reduction theory, revealing its degradation under asymmetric sampling slew rates. The phase- and voltage-domain models validate each other and offer useful guide for DSPLLs design optimization.
