Article ID: 23.20260002
Compared with single-edge designs, dual-edge-triggered flip-flops (DETFFs) can maintain the same data throughput while operating at half the clock frequency. However, when integrating ferroelectric nonvolatile structures with selector-based DETFFs, the uncertain logic levels of the clock and data signals during the restore phase may lead to unintended ferroelectric field-effect transistor(FeFET) programming. In addition, conventional C-element-based flip-flops suffer from limited performance. To address these issues, this paper presents an input C-element design that enforces input isolation by generating complementary outputs during the restore process, along with an improved output C-element. Experimental results show that, compared with existing C-element-based flip-flops, The proposed design reduces operating power by at least 33.3%, and decreases hold time by at least 58.8%. In addition, the clock-to-Q delay is reduced by at least 9.2%. The proposed flip-flop is capable of storing its output state prior to power-off and effectively isolating both data and clock signals during restoration, enabling accurate recovery of the pre-shutdown state while improving C-element performance.
