Article ID: 23.20260004
Power consumption is a critical challenge in integrated circuit (IC) design. Since post-synthesis power simulation is time-consuming, fast and accurate pre-synthesis power estimation, especially at the register-transfer level (RTL) stage, is essential for guiding power optimization. However, existing RTL-stage power models struggle to simultaneously achieve cross-design generality and time-based resolution, and often rely on large-scale labeled training datasets. We present AtomPower, a general machine-learning (ML)-based power modeling framework for per-cycle power estimation across diverse RTL designs. AtomPower introduces the register structure tree (RST) to decompose a circuit into a fine-grained, bit-level structural representation, enabling accurate time-based power modeling. To address multicollinearity in regression and derive reliable power labels, we develop a finite greedy clustering (FGC) algorithm that specializes conventional clustering methods by incorporating structural constraints. In addition, we propose a tailored data augmentation strategy to significantly reduce the reliance on large labeled datasets during training. Evaluated on a diverse set of designs, AtomPower achieves a Mean Absolute Percentage Error (MAPE) of 5.02% and a correlation coefficient (R) of 0.85, outperforming state-of-the-art RTL-stage power models in both estimation accuracy and data efficiency.
