Page Table Level Aware Buddy System for TLB Coalescing

Abstract

The efficient physical memory allocation is essential for high performance, particularly in architectures that support translation look-aside buffer (TLB) coalescing. The binary buddy system (BBS) is a widely used page allocator that operates in the block level. However, it enforces rigid power-of-2 block size constraints. This constraint undesirably incurs memory fragmentation and can degrade the memory system performance. To resolve this issue, we propose an architecture-specific allocator, namely a page-table level aware buddy system (LBS). Considering modern embedded system on a chip (SoC), where input/output (I/O) devices run high-bandwidth 2D data applications, we present the algorithm, an analysis, and performance experiments. The experiments indicate that, by integrating TLB coalescing, LBS can significantly reduce fragmentation and improve memory system performance.