A Foreground NVD Calibration with coarse DACs for High-Precision Noise-Shaping Pipeline SAR ADCs

Abstract

This article presents a foreground calibration technique to mitigate the interstage gain error induced by the non-ideal voltage division (NVD) effect in noise-shaping (NS) pipeline successive-approximation-register analog-to-digital converters (SAR ADCs). The proposed method employs a hybrid-domain feedback loop that adjusts the reference voltage via 9-bit coarse digital-to-analog converters (DAC), effectively suppressing the leakage of first-stage quantization noise without requiring invasive modifications to the core analog path. To ensure long-term stability against charge leakage at high-impedance nodes, a periodic refresh strategy is implemented with negligible power overhead. Furthermore, a comparator reuse technique is adopted to eliminate offset errors. Validated in 40-nm complementary metal-oxide-semiconductor (CMOS) technology, the calibration improves the signal-to-quantization-noise ratio (SQNR) from 76.57 dB to 90.30 dB and achieves a spurious-free dynamic range (SFDR) of 95.77 dBc. The robustness of the proposed technique is verified by Monte Carlo analysis, demonstrating a post-calibration gain accuracy of 0.2% (3σ).