A 9-to-13 GHz CPPLL with -72.27 dBc reference spur, 80.9 fs_rms jitter and -246.9 dB FoM in 65-nm CMOS process

Abstract

The growth in 5G mm-Wave communications draws tremendous demands on the high-quality signal sources. To satisfy the requirements for a wide tuning range and low phase noise, PLL cascaded with a frequency multiplier is typically applied in mm-Wave systems. In this letter, a 9-13 GHz integer-N charge-pump PLL (CPPLL) is designed, which could cooperate with a frequency tripler and a 6-GHz intermediate frequency to fully cover the 5G mm-wave FR2 frequency bands. In the PLL design, a parallel inductor is used in the voltage-controlled oscillator (VCO) to avoid its Q-factor degradation, thus improving the phase noise performance. Additionally, thick-oxide transistors are employed to extend the CP output voltage range, which could increase the PLL tuning range with a relatively small varactor, and in turn improve the VCO tank Q-factor. Besides, the small varactor could reduce the VCO gain, which can suppress the reference spur. The proposed CPPLL is fabricated in a 65-nm CMOS process with a core area of 2.6 mm². With measurements, the PLL demonstrates a 36.36% frequency tuning range from 9 to 13 GHz, and achieves a jitter of 80.9 fs and a reference spur level of -72.27 dBc. With a typical power consumption of 31.2 mW, the CPPLL achieves -246.9 and -241.8 dB figure of merit (FoM) and figure of merit with tuning range (FoM_T), respectively.