Frequency-variable subsystem for 15GHz high-performance broadband RF synthesizer with ultra-wide dynamic range frequency divider and multiplier sub-circuit

Abstract

This paper proposes a frequency-variable subsystem for a 15GHz high-performance broadband RF synthesizer. The subsystem integrates a 2 - 1025 frequency division ratio range divider (PRE_R_DIV), a 2 - 31 ratio frequency multiplier (MULT), an XOR-logic based frequency doubler (2X) circuit, and a 2 - 255 frequency division ratio divider (POST_R_DIV) with standard CMOS gate logic to generate appropriate PFD frequency (f_PFD) through frequency division and multiplication combinations. This ensures the f_VCO is not integer multiple of f_PFD, suppressing integer boundary spurious (IBS) obviously. The chip is manufactured by 40-nm CMOS technology and each sub-circuit can be enabled or disabled through designed bypass configuration. As input frequency is 200MHz and the output is 15GHz, with equivalent calculation, measurement results show subsystem achieved -150.54dBc/Hz at 1MHz phase noise performance while all sub-circuits enabled, -151.18dBc/Hz at 1MHz phase noise when they are bypassed. Results also show that the suppression of spur power at least 8dB.