Design of CMOS Chip for Multi-functional Distributed Brain Machine Interface System

Abstract

This letter proposes a multifunctional distributed Brain-Machine Interface (BMI) system. The system achieves bidirectional communication and power delivery over a single shared coaxial network. To realize multi-functionality, four stimulation and recording functions were integrated into a CMOS core chip fabricated in a 180 nm standard process. A 23.5 x 7.5 mm prototype unit device was fabricated for functional verification. Results demonstrated 40 µA-resolution stimulation and an input-referred noise of 125 µV_RMS. Furthermore, simultaneous operation of two unit devices was verified, confirming the architecture's scalability. This work provides a versatile platform for multi-point neural interfacing with minimal wiring.