Low-resource TRNG with variable entropy sources based on TDC

Abstract

The extraction of entropy sources is a challenging task in TRNG design. In this paper, a novel entropy extraction circuit based on time-to-digital converter is proposed to extract the entropy source by jitter randomness of Carry4 composition. The proposed architecture is validated on three series of Field-Programmable Gate Arrays (FPGAs): Xilinx Spartan-6, Artix-7, and Virtex-6. It selects two different frequency Ring Oscillators (RO) for entropy extraction and utilizes a five-stage DFF chain for post-processing. The random numbers generated by the TRNG proposed in this paper passed NIST SP 800-22, portability test, temperature and voltage test, autocorrelation test, AIS-31, and TEST U01 with relatively excellent results. It is worth mentioning that the TRNG architecture in this paper, including post-processing, only uses 8 LUTs, 15 DFFs, 16 registers, 2 Carry4, and achieves a throughput of 300Mbps.