A 92.5-dB SNDR 100-kHz BW Discrete-Time ΔΣ ADC with Parallel-Body-Biased FIA and Floating-FVF-Based Noise-Shaping SAR Quantizer

Abstract

This letter presents a discrete-time (DT) 3^rd-order ΔΣ ADC with a 4-bit noise-shaping SAR (NS-SAR) quantizer. A parallel-body-biased floating inverter amplifier is proposed, achieving competitive noise performance. In addition, a low-power floating flipped voltage follower (FFVF) is proposed for the NS-SAR quantizer, reducing power consumption by 22% compared to a conventional dynamic FVF design. Fabricated in a 65-nm CMOS technology, the prototype DT ΔΣ ADC achieves an SNR of 92.9 dB, an SNDR of 92.5 dB, an SFDR of 113.4 dB, and a DR of 93.2 dB with 100 kHz BW, while consuming 127.8 μW at a sampling rate of 10 MHz. This corresponds to an SNDR-based Schreier FoM of 181.4 dB and a DR-based Schreier FoM of 182.1 dB.