最小経路数に基づく構造探索を導入したブロック構造ニューラルネットワーク学習法

抄録

In recent years a study of evolvable hardware (EHW) which can adapt to new and unknown environments attracts much attention among hardware designers. EHW is reconfigurable hardware and can be implemented combining reconfigurable devices such as FPGA (Field Programmable Gate Array) and evolutionary computation such as Genetic Algorithms (GAs). As such research of EHW, Block-Based Neural Networks (BBNNs) have been proposed. BBNNs have simplified network structures and their weights and network structure can be optimized at the same time using GAs. The learning of BBNNs without constraint of network structures is, however, not efficient because the degree of difficulty of learning depends on network structures. In this paper, we propose a new evaluation index of network structures for BBNNs based on the least number of routes which are from inputs to outputs, and apply it to the structure search. The learning of BBNNs is efficiently executed with structure constraint condition based on the proposed index because the network structures which are difficult to learn are excluded. In order to evaluate the proposed method, we apply it to XOR, 3 bit-parity, square function approximation, contact lenses fitting, Fisher's iris classification and Wine classification. Results of computational experiments indicate the validity of the proposed method.