低消費電力軽量暗号Midoriに対する階層的電力解析とその評価

抄録

The illegal attacks for embedded devices have recently been reported. Therefore, lightweight block ciphers, which are suitable for embedded devices, have been attracted attention. Midori is a lightweight low power block cipher. Regarding the hardware security, the risk of power analysis for the cryptographic hardware is pointed out. Hence, the tamper resistance evaluation of a lightweight low power cipher Midori is very important to guarantee the security of embedded devices. However, power analysis of Midori has not been studied. Therefore, this study proposes a new power analysis method for Midori. The proposed method performs the hierarchical power analysis to analyze the all secret keys. Moreover, to reduce the computational complexity, the proposed method performs the efficient improvement method utilizing the characteristic of Midori algorithm. Experiments using a field programmable gate array prove the validity of the proposed method.