電気学会論文誌C(電子・情報・システム部門誌)
Online ISSN : 1348-8155
Print ISSN : 0385-4221
ISSN-L : 0385-4221
<電気回路・電子回路>
Multiplied ΔΣ Time to Digital ConverterのNoise shaping改善の検討
嘉藤 貴博安田 彰
著者情報
キーワード: TDC, PLL, ΔΣ, DEM, ループ帯域, ジッタ
ジャーナル 認証あり

2021 年 141 巻 1 号 p. 37-43

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Previously, the method has been proposed to reduce the quantization noise of the fractional N-PLL and the spurious due to the reference leak by placing a DLL before the PLL. We have previously proposed Multiplied ΔΣTDC, which solves the phase noise problem and spurious due to DLL delay device manufacturing variation. However, in the previous proposal, there was a trade-off between spurious reduction and quantization noise improvement by ΔΣTDC. In this paper, we propose a Multiplied ΔΣTDC that solves this problem and always has the effect of Noise shaping by ΔΣTDC.

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