遺伝的状態生成処理を取入れた改良型アニーリング法によるフロアプラン

抄録

This paper proposes an improved simulated annealing method based on genetic algorithm and applies it to a floorplan design of VLSI. The proposed method can effectively search wide state space for an optimal solution because of the parallel search starting from many initial points and the genetic selection among its paths. Computational experiments show that this method is more powerful to get a better solution than conventional simulated annealing method.