抄録
Using PARTHENON, a CAD (Computer Aided Design) software system, we design five kinds of fixed point divider, one floating point divider, and synthesize their logic circuits. We compare our designed circuits in point of the numbers of gates, area, power consumption and the maximum of rising delay.
As a results, in case of fixed point division circuits, the gate numbers in each circuits is expressed with their division bits and different variables. The delay time increase depends on the division bits increase, but its increasing rate is difference by different circuits.
The floating point divider was implemented by index calculation, extra process, rounding process to the fixed point divider. The delay time in the floating point divider is longer than that in the fixed point divider only by the amount of time needed to perform the added process.
