抄録
Waveform distortion at signal edge generally falls into two categories: hysteresis type and non hysteresis type. Non hysteresis type distortion has a flat portion in signal transition, but it will not give any serious problem except for timing oriented circuits. While, hysteresis type distortion which makes round trip between two threshold levels will affect logic judgment. Incorrect information will be transmitted if signal is seriously distorted. It is important to understand relationship between spectrum modification and waveform distortion.
In this paper, an occurrence mechanism for the output waveform distortion of CMOS logic ICs are analyzed and improving method for them are proposed. Waveform distortion occurs when series resonance circuits are composed at load side of driving device. Relationship between rising time/period [%] and limit frequency at which waveform distortion begin to appear will be made clear. There are two method to improve waveform distortion. One is to change spectrum distribution of rectangular wave by modifying rising time. The other is to change resonance frequency by modifying such parasitic elements as inductance (pattern length) and capacitance (amount of ICs).
