抄録
In a large scale broadband communication system, thousands of high-speed serial data interconnections are used and a bit synchronization circuit (a clock and data recovery circuit) is required in each of the receiver side interconnection circuit. In this paper, the requirements and the implementation of a bit synchronization circuit for the interconnection are considered, and one solution is proposed. In the proposed circuit, the oscillation phase of a VCO is directly controlled by the trigger signal extracted from the input data. Synchronization capturing is quick and the circuit is applicable to a burst signal. The circuit tolerates jitter and phase variation of the incoming data. The circuit requires no external components, and is suitable for an integrated circuit. The circuit has been implemented using a 0.5um CMOS process and the data recovery operation from a 440Mbps pseudo-random pattern was confirmed. Data acquisition is accomplished within three clock periods from a 440Mbps burst data.
