抄録
In this paper, we propose a novel parallel multiplication scheme using 2×2 submultipliers. It adopts a new encoding method which halves the number of partical products through 2×2 submultipliers and rearrangement of primitive partical products. We present the parallel multiplication algorithm and design a 16bit×16bit multiplier architecture of the proposed method, which is suitable for VLSI implementation. The proposed scheme can be easily extended to large-size multipliers with 32, 54 or even longer bits. This parallel mltiplication scheme can be applied to many areas such as DSP, MPEG and so on.
