列型FPGAの低消費電力指向配置・概略配線手法

抄録

FPGA is now being watched with interest as VLSI which user can realize for a short term. Besides, by reason of popularization of portable application with a battery, power optimization is rapidly becoming very important for the design of VLSI. We propose a simultaneous placement and global routing algorithm for row-based FPGAs with critical path delay and power optimization. In the proposed method, the critical path delay is estimated based on Elmore delay model, and the power consumption is evaluated based on the switching activity of nets. The experimental results demonstrate the efficiency and effectiveness of the proposed method.