抄録
This paper discusses the novel approach to solve the VLSI channel problem. Routing is one of the major tasks in the physical design of VLSI. Terminals that belong to the same net are connected together subject to a set of routing constraints. With new performance requirements for the design. routing constraints such as crosstalk and RC delay between interconnections are becoming increasingly dominant in submicron regimes. Crosstalk is delay due to coupled capacitance and RC delay is caused resistance and capacitance. Hence, the proposed algorithm based on Genetic Algorithms optimizes both physical constraints (number of tracks) and electrical constrains (crosstalk and RC delay). For selection control, which is one of the genetic operations, new objective functions for minimum crosstalk and RC delay are introduced in addition to the usual objective function based on number of tracks. The experimental results prove that the proposed algorithms is effective for reducing crosstalk and RC delay, as well as number of tracks.
