A Test Program Generation for Scalable SIMD Parallel Computer

抄録

Computer hardware testing is performed with test, programs generated by using machine instructions or high-level language. A parallel computer is characterized by the complexity resulting from its system configuration consisting of an array of a number of processors, and also by the parallel processing unit whose hardware configuration can be varied corresponding to the system objects and the required performance conditions. Because of this, it is required to prepare the test. programs corresponding to the respective hardware configurations. This means that the number of test programs required increases with the number of hardware configuration types designed, and this requires a tremendous amount of labor for their generation.
This paper proposes a system for efficiently generating the test programs to be used for hardware testing of the scalable SIMD parallel computer. This system makes the most of the functions and features of the scalable SIMD parallel computer, and generates the test programs without depending on the hardware configuration of the parallel processing unit. By using this system, it is possible to reduce the types and number of the test programs, and consequently, the period for the development.