Turn On/Off Delay Time Control for Current Balancing in Parallel Connected IGBTs without Increasing Switching Loss

Abstract

In this letter, a turn on/off delay time control for current balancing in parallel connected IGBTs, without increasing a switching loss, that uses a dynamically adjustable gate resistance (R_g) is presented. By dynamically adjusting the gate resistance within a switching period, the turn-on/off delay time can be controlled without affecting dI_C/dt and dV_CE/dt. Therefore, the reduction in dI_C/dt and dV_CE/dt due to the increase in the gate resistance is suppressed. This leads to the successful correction of the current imbalance during the switching transient among IGBTs in the module, without increasing the switching loss.