2025 年 14 巻 6 号 p. 1065-1073
A power transistor utilizing a Darlington configuration of a Si-superjunction bipolar junction transistor (Si-SJBJT) as the main transistor and a Si-superjunction MOSFET (Si-SJMOSFET) as the auxiliary transistor, referred to as the Si full SJBMD, is proposed. A 10A sample of the full SJBMD with a breakdown voltage of 625V was developed, in which both the SJBJT die and the SJMOSFET one were assembly in a TO-247-4L package. The sample includes a main gate terminal, as well as an auxiliary gate terminal designed to extract stored charge from the main SJBJT during the turn-off operation. The VCE(sat) at the rated current of the full SJBMD is 1.22V at room temperature. Increasing negative gate voltage in a charge extraction circuit connected to the auxiliary gate effectively decreases the power loss and delay time during the turn-off operation of the full SJBMD. Simulations compared the trade-off relationship between switching loss and on-state voltage of the full SJBMD with that of the competitive transistors. Additionally, impacts of the negative gate voltage in the charge extraction circuit on the SOA, as well as impacts of the shunt resistance connected between the auxiliary gate and emitter on the SOA and VCE(sat) were clarified.
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