Voltage Harmonic Analysis of Typical PWM Strategies in a Dual Inverter with Floating Capacitor in the Partial-Load Condition

抄録

This study aims to reduce the voltage harmonics, caused by pulse width modulation (PWM) in a dual inverter with a floating capacitor topology in the partial-load condition. This work provides an analysis strategy for the output voltage harmonics, which depend on the fundamental voltage, power factor angle, and PWM strategies. Herein, sinusoidal PWM (SPWM), third harmonic injection PWM (THIPWM), and discontinuous PWM (DPWM) are used as the conventional carrier-based modulation techniques, and space vector PWM (SVPWM) and near-state PWM (NSPWM) with reduced number of commutations are used as the proposed modulation methods. The validity of the theoretical analysis is then confirmed by experiments using an open-end winding induction motor. The voltage total harmonic distortion (THD) is reduced by maximizing the modulation indices of both inverters in each modulation method; the experimental results show that voltage THD reductions of 10.9% with NSPWM and 17.3% with SVPWM can be obtained compared with that of SPWM. The total efficiency, including the inverter and motor efficiencies, is improved by up to 2.6% in the low load region (at a torque of 0.5 Nm and fundamental frequency of 10 Hz) when using the SVPWM.