Gate Driver ICs with Closed-Loop Current Balancing Control for Parallel Connected IGBTs

抄録

This study proposes a closed-loop current balancing control scheme for mitigating the current imbalance during switching intervals between IGBTs connected in parallel. The proposed control technique is based on a current balancing control scheme that utilizes a gate driver circuit, in which the output resistance can be varied using a segmented gate driver technique. Moreover, it reduces the current imbalance by minimizing the delay time difference between IGBTs connected in parallel.

Gate driver ICs equipped with the closed-loop current balance controller is also proposed and fabricated using XFAB's 0.35 μm HV CMOS process. To verify the effectiveness of the closed-loop current balancing control, a multi-pulse switching test is conducted with a PCB test board comprising a simple chopper circuit with two parallel connected IGBTs rated at 600 V and 90 A. The test results reveal that the current balance controller determines and controls the output resistance of the gate driver ICs, thereby significantly reducing the current imbalance between parallel connected IGBTs during the switching transient.