Parasitic Inductance Characterization of Full-Bridge Power Module Based on S-Parameter Measurements

抄録

The operation of SiC MOSFETs with high 𝑑𝑖/𝑑𝑡 and 𝑑𝑣/𝑑𝑡, coupled with high parasitic oscillation frequency due to low device parasitic capacitances, can increase electromagnetic interference (EMI) noise in the high-frequency region. For the prediction of conducted EMI emissions, analytical models are preferred. However, they require accurate circuit switching transients and noise-propagation path parasitics modeling. To analytically model device switching transients, circuit parasitics values are required. Despite their importance, complete parasitic models of power modules are rarely provided by manufacturers. In this study, a wiring parasitic inductance characterization method for a full-bridge power module, based on 4-port S-parameter measurements, is proposed. A numerical model of power module wiring parasitics is presented and experimental S-parameter data is used to calculate parasitic inductances. These calculated parasitics values are validated by comparing them with FEM simulation results.