Thick Oxide Layer Fabrication Process for Silicon RF ICs

Abstract

We present a new method to reduce substrate losses and parasitic capacitances of passive elements on silicon RF ICs. The method is based on a fabrication process to selectively bury thick oxide layer regions in a silicon substrate. The process consists of two steps, such as high aspect-ratio trench forming using a D-RIE (Deep Reactive Ion Etching) technique, high temperature oxidation in a wet environment, polycrystalline silicon deposition and etching. This is also CMOS compatible one.
Using the method, we have succeeded in fabrication of 25μm thick oxide layer regions in a silicon substrate. The maximum Q value of a spiral inductor on the thick oxide layer has been improved twice as large as one on a field oxide layer fabricated by a conventional CMOS process. In addition, the power consumption of a 1.6GHz VCO (Voltage Controlled Oscillator) using the spiral inductor on the thick oxide layer has been reduced by 40% compared with the one by conventional technologies.