電気学会論文誌E(センサ・マイクロマシン部門誌)
Online ISSN : 1347-5525
Print ISSN : 1341-8939
ISSN-L : 1341-8939
論文
Consumer Electronics 高密度化のためのビア積層の影響
中西 徹長谷 智弘
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2008 年 128 巻 12 号 p. 493-498

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The stacked via technology becomes to be one of key technologies for the achievement of high density packaging as of today, however, it could not be said that the influence of via stacking has been understood sufficiently. The influence of one to five stacked VIA technologies are studied with the parameter of stress and strain on the view point of reliability, comparing the condition that these vias are located directly on the RFP (Resin Filled PTH (Pin Through Hole)), and the other condition that these are located left and right with some distance from RFP. The maximum is happened at the smallest neck of via, and it is recommended that the via stacking is designed with some distance from RFP. The guideline as to the optimized design of the substrate that has the stacked via is provided.

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© 電気学会 2008
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