An Efficient Design of 45nm Charge-Pump Phase-Locked Loop Architecture for Sub-1G IoT Applications

Abstract

Amid the rapid advancements in technology, the Internet of Things (IoT) has become a pivotal element in the realm of wireless communication. The sub-1GHz network, in comparison to its higher frequency counterparts for IoT endeavors, offers distinct advantages, including extended range and reduced power consumption. Recognizing the critical role of phase-locked loops (PLLs) in enhancing data transceiver and communication systems, this study presents a charge-pump phase-locked loop (CPPLL) designed specifically for sub-1G IoT deployments. Utilizing a 1.0 V input voltage alongside a modest 20 MHz reference frequency, our PLL architecture is developed utilizing 45 nm technology from the NCSU process. According to simulations conducted on the Cadence Virtuoso platform, our CPPLL design achieves an output frequency range of 467.3 to 877.2 MHz and an RMS jitter of 150 ps, demonstrating its potential effectiveness for sub-1G IoT systems.