Design of a Motion Stereo VLSI Processor Based on a Transfer Bottleneck-Free Sensor/Memory Architecture

Abstract

This paper presents an architecture for parallel image processing that breaks the bottleneck of data transfer between an image sensor, memories and functional units. By employing an integrated image sensor, parallel data transfer between the sensor and memories can be achieved. Moreover, for parallel memory access, an optimal memory allocation is proposed that maps pixels to be accessed in parallel onto different memory modules. A functional unit allocation for local communication is also proposed to minimize the complexity of the interconnection network between memories and functional units.