抄録
A vision chip employing pulse width modulation(PWM) circuitry in each pixel is designed and fabricated. The neighboring pixels are interconnected with active resistors to diffuse noise, which is effective to decrease fixed pattern noise from 1% to 0.2%. By using this PWM technique it is demonstrated that histogram equalization and A/D conversion can be simultaneously realized during accumulation period. A comparator, which is used for the PWM operation, consists of one capacitor and three transistors and has A/D conversion of 7-bit precision in 2 msec. 1.2μm CMOS 2-poly 2-metal process is used to fabricate the chip, which has 16 × 16 pixels with the pixel size of 158μm × 103μm. The power consumption is 300μW per pixel in the processing speed of 500 frames per second.
