Hardware Design and Implementation of IP-over-1394 Protocol Stack and Its Evaluation

抄録

This paper describes a hardware design of a subset of the Internet protocol IP over IEEE1394 interface (IP over 1394) and its implementation on an FPGA. It evaluates the design by counting the hardware costs required for the implementation. It is intended for use in such applications as home networks, where transferring and processing digital AV data at low costs and by low power consumption is desirable. Using a system clock of 49.152MHz, we verified that packets sent from an application on top of the protocol stack were correctly received by the other protocol stack via IEEE1394 port at a transfer rate of 400 Mbps. We also verified communication behaviors of the design with an isochronous resource manager to reserve a channel prior to data transmissions. The hardware cost of the IP layer is 84% of the link layer's cost, meaning that the IP-over-1394 protocol stack can be realized by hardware by spending an extra cost less than that of the basic hardware which already exists.