A High-speed Low-power CMOS Image Sensor with Delta and Interpolation Readout Scheme

抄録

This paper presents a high-speed low-power readout scheme for CMOS image sensors (CISs) that utilizes the image properties. The proposed delta and interpolation readout (DI-readout) scheme reads the signal difference between two adjacent pixels (Δpixel) by utilizing MSBs information of the previous pixel, using large Δpixel for interpolation and small Δpixel for delta readout. By effectively reducing the dynamic range of the signal, the proposed readout scheme can reduce the number of decision cycles and the power consumption of SAR ADC. A prototype QQVGA CIS with ten 10-bit SAR ADCs was fabricated in a 0.18 μm 1P4M CIS process with a 4.4 μm pixel pitch. The measurement results of the implemented prototype CIS showed a figure-of-merit (FoM) for imager of 0.35 e-nJ.