自己組織化マップを用いたFPGA配置の高速化手法

抄録

A placement process is one of the heavily computational process in FPGA(Field Programmable Gate Array) design flow. Although nondeterministic algorithms such as SA(Simulated Annealing) algorithm are successful in solving this problem, they are known to be slow. We have been introduced neural network approach which is a Kohonen SOM(Self Organizing feature Maps) to FPGA placement. In this paper, we proposed input vector based on a shimbel index. Our method can improve computational time compared with SA based VPR using some benchmark circuits in the evaluation.