LUTベースのFPGAにおけるテクノロジーマッピングのノードカバー数の評価

抄録

Technology mapping is a crucial step in FPGA design, where a combinational circuit is represented using LUTs. The latest technology mapper ABC uses the And-Inverter-Graph (AIG) to represent the circuit and aims to minimize the number of LUTs required to cover each node (representing an AND gate) in the graph. However, due to heuristics in ABC, the number of LUTs may not necessarily be the minimum. We propose the node cover count as an evaluation metric for the mapping, indicating the average number of AND gates covered by a single LUT. We evaluate the technology mapping based on this metric.