オリジナルFPGA-IPへのオープンソース論理合成ツールの適用

抄録

We developed an original FPGA-IP for MEC devices. The current design flow includes ODIN II and YOSYS front-end as logic synthesizer. However, the combination of ODIN II and YOSYS has caused several serious problems in our EDA flow. We rearranged and adopted only YOSYS　as a logic synthesizer for our FPGA-IP includes some hard macros. The circuit design for our original FPGA-IP can be performed with a new rearranged EDA flow.