A High-Signal-Integrity PCB Trace with Embedded Chip Capacitors and Its Design Methodology Using a Genetic Algorithm

抄録

Signal integrity (SI) degradation in printed circuit boards (PCBs) in the gigahertz domain has become an increasingly serious problem because of the difficulty of developing and implementing impedance matching designs. In this paper, we propose a novel trace structure called a capacitor segmental transmission line (C-STL) and a design methodology for C-STL capacitances to overcome the problem of SI degradation. In a C-STL, reflected waves are intentionally generated by mismatching the impedance of adjacent segments with embedded chip capacitors connected to the PCB trace. These reflected waves interfere with the distorted digital signal and shape it into an ideal waveform. In the proposed C-STL design methodology, a genetic algorithm is used to overcome the combinatorial explosion problem posed by the chip capacitor selection required in the design. A C-STL prototype was fabricated, and its high SI improvement capabilities were demonstrated by eye diagram measurements.