Transactions of The Japan Institute of Electronics Packaging
Online ISSN : 1884-8028
Print ISSN : 1883-3365
ISSN-L : 1883-3365
Short Note
Fabrication of Multi-stacked Integrated Circuit for High-Performance Image Sensors
Naoki NakataniYuki HondaMasahide GotoToshihisa WatabeMasakazu NanbaYoshinori IguchiTakuya SarayaMasaharu KobayashiEiji HigurashiHiroshi ToshiyoshiToshiro Hiramoto
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2020 Volume 13 Pages E20-004-1-E20-004-3

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Abstract

We have been developing a three-dimensionally (3D) structured complementary metal-oxide semiconductor (CMOS) image sensor (CIS), which has individual signal processing circuits in each pixel under the photoelectronic conversion area for high-performance and multi-functional operation. In this paper, we report on our experimental 3D integrated circuits developed using multi-stack technology, which enables us to fabricate 3D-CISs with small pixels. The results showed the fundamental operation of the prototype circuit, which indicates the feasibility of highly integrated 3D-CIS of More-than-Moore type applications.

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© 2020 The Japan Institute of Electronics Packaging
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