抄録
In this paper, the broadband low ripple digital PLL (phase locked loop) circuit using clock generator with frequency follow-up control was constructed by utilizing the fact that the capture range of digital PLL becomes scalable when changing the frequency of the basic clock generator. The modeling and analysis are done on dynamical system simulator. This digital PLL has achieved tracking frequency range of 10 Hz to 10 kHz and proven that the phase error ripple can be controlled as designed.
