日本ロボット学会誌
Online ISSN : 1884-7145
Print ISSN : 0289-1824
ISSN-L : 0289-1824
再構成可能並列プロセッサと知能ロボット制御への応用
藤岡 与周亀山 充隆苫米地 宣裕
著者情報
ジャーナル フリー

1995 年 13 巻 6 号 p. 846-853

詳細
抄録

In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of arithmetic operations. In addition to many multiply-additions, the arithmetic operations such as absolute value calculation and maximum value selection are often used in the dynamic control of robot manipulators. To reduce the delay time for multi-operand arithmetic operations, the architecture of the reconfigurable parallel processor is proposed. In each processor element, a switch circuit is used to change the connection between the multipliers, adders and arithmetic units (AUs), so that the multi-operand AUs having desired numbers of operands can be reconfigured. Since the data transfer is accomplished by the direct connection between the multipliers, adders and AUs, the overhead for data transfer is reduced. The chip evaluation based on 0.8 [μm] CMOS design rule shows that the delay time for differential inverse kinematics computation and inverse dynamics computation of a six-degrees-of freedom manipulator become 1.7 [μsec] and 11.5 [μsec], respectively.

著者関連情報
© 社団法人 日本ロボット学会
前の記事 次の記事
feedback
Top