抄録
In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of arithmetic operations. In addition to many multiply-additions, the arithmetic operations such as absolute value calculation and maximum value selection are often used in the dynamic control of robot manipulators. To reduce the delay time for multi-operand arithmetic operations, the architecture of the reconfigurable parallel processor is proposed. In each processor element, a switch circuit is used to change the connection between the multipliers, adders and arithmetic units (AUs), so that the multi-operand AUs having desired numbers of operands can be reconfigured. Since the data transfer is accomplished by the direct connection between the multipliers, adders and AUs, the overhead for data transfer is reduced. The chip evaluation based on 0.8 [μm] CMOS design rule shows that the delay time for differential inverse kinematics computation and inverse dynamics computation of a six-degrees-of freedom manipulator become 1.7 [μsec] and 11.5 [μsec], respectively.
