抄録
This paper presents a design methodology for high-speed sequential circuits. As high-density integrated circuit technology advances, the number of transistor cells in a circuit is becoming unimportant. To minimize the circuit depth, it is necessary to find locally dependent information. A transition graph representation of partition pairs is obtained from state sets of a sequential circuit, using the concept of multi-block partitions. An algorithm is proposed for minimizing the code length in the minimum logic depth of the state transition functions, by efficiently dividing multi-block partitions into two blocks.
