抄録
Many models have been proposed for simulation of planarization process of patterned Si wafer. In the previous report, an analytical model has been established to incorporate variations in pattern density, step height of an oxide layout, the tool stiffness and in feed scheme. In this paper, we aimed to further improving the accuracy of the simulation via introducing an actual oxide layout. Instead of a rectangular layout, a triangular layout with multi-step height was used for the simulation model to clarify the effect of pattern profile.
