FPGA Implementation of Single-Image Super-Resolution Based on Frame-Bufferless Box Filtering

Yuki Sanada; Takanori Ohira; Satoshi Chikuda; Masaki Igarashi; Masayuki Ikebe; Tetsuya Asai; Masato Motomura

doi:10.2299/jsp.17.111

Yuki Sanada, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura

著者情報

ジャーナルフリー

2013 年 17 巻 4 号 p. 111-114

DOI https://doi.org/10.2299/jsp.17.111

詳細

抄録

Recently, a novel algorithm of filter-based single-image super-resolution (SR) has been proposed. We here propose a hardware-oriented image-enlargement algorithm for the SR algorithm based on frame-bufferless box filtering, and present novel circuits of the proposed enlargement algorithm and the SR algorithm for an field-programmable gate array (FPGA), aiming at the development of single-image SR module for practical embedded systems.

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