Since the conventional strategy, namely scaling of device dimensions in ultimately scaled shorter-channel-length MOS transistors, is less effective to enhance transistor performance, another strategy is strongly demanded. Stress engineering is one of the most promising performance boosters for the ultimately scaled MOS transistors. In this paper, we will introduce the physical mechanisms of the drain current enhancement induced by stress. We will discuss the mechanisms based on the band structure modification by stress. The effectiveness of the stress engineering in future devices is also prospected.
