Pattern Design to Prevent Sawing-Induced Passivation Damage on Scribe Region During Semiconductor Wafer Separation
2018 Volume 59 Issue 12 Pages 1887-1891
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2018 Volume 59 Issue 12 Pages 1887-1891
This work details how devices mechanically separated from wafers with a dummy pattern in their scribe region can undergo serious reliability degradation due to Si3N4 damage. Experimentally, it was found that although chipping damage occurs only within the scribe region, Si3N4 damage can grow up to the active region, which is far away, beyond the chipping damage range, because inappropriate Si3N4 coverage in the scribe region can be a carrier for damage propagation during sawing. Further, this work shows that Si3N4 damage existing in the scribe region even after wafer separation completion can further attack the active region and cause device failure during thermal-cycling. So, this work suggests that appropriate design of the amorphous Si3N4 layer in the scribe region is essential in order to allow the devices to have better reliability margins during thermal-cycling as well as mechanical wafer separation.
In recent semiconductor products, passivation layers to protect its underlying metallic conductor have been thinner up to a thickness smaller than 0.3 um for more compact electronic pattern, while the mechanical sawing is still widely-used for wafer dicing. Thus, sawing-driven reliability degradation has been one of the most key challenges in making reliable semiconductor devices.1–11) However, it is not known how the layout structure of passivated patterns (i.e., dummy patterns) in the scribe regions, which exist between active device regions to allow cutting of the semiconductor wafers into individual devices, influences the reliability of diced devices after the mechanical sawing of the semiconductor wafers.
Indeed, TEG (test element group) patterns are usually formed in scribe regions in order to obtain various useful information at the wafer level. Since the TEG patterns are unnecessary for individual devices, they can be destroyed during wafer separation. However, if an individually diced device includes TEG pattern-related defects that survived after wafer dicing, these can be sources of serious reliability problems.5,6,11) Therefore, it is necessary to elucidate how the layout structure of the TEG pattern correlates with sawing-induced damage. Particularly, since the passivation layer, which is the top layer of the TEG pattern, is composed of a brittle material such as amorphous Si3N4, it is very susceptible to brittle fracture in use. Thus, this article focuses on how effectively a change in the layout structure of the passivated TEG pattern in the scribe region can suppress the initiation or propagation of pattern damage during thermal-cycling as well as wafer separation.
The active regions of 12-inch silicon wafers were initially coated with thermally grown oxide (SiO2) to a thickness of 1 µm. Then, aluminum based metallic conductors were sputter-deposited to a thickness of 0.6 µm. This was followed by the deposition of passivation materials (i.e., Si3N4) up to a thickness of 0.3 µm.5) The Si3N4 layer has a non-crystal structure. However, the layout of the Si3N4 layers in the scribe regions was designed to have 3 different structures, as shown in Fig. 1. The A group was prepared to have no Si3N4 layer on the scribe regions, as shown in Fig. 1(a). The B group was prepared to have Si3N4 layer on one half of the scribe region, as shown in Fig. 1(b). And the C group was prepared to have Si3N4 layer on the whole surface, including scribe regions, as shown in Fig. 1(c). Using a diamond-pointed saw blade for the dicing process, all test wafers were diced into individual devices whose thickness was approximately 15 µm, as shown in Fig. 2.6) The revolving velocity of the saw blade was increased from 10000 rpm to 60000 rpm to study the effect of sawing velocity variation on pattern damage during thermal-cycling as well as wafer separation. Individually diced chips have appropriate dimensions of 5 mm × 10 mm × 0.2 mm. All diced chips were plastically-encapsulated utilizing an LOC (lead-on-chip) die attach technique, as shown in Fig. 3. The package dimensions are approximately 6 mm × 12 mm × 0.4 mm. For the reliability test of the chips with sawing-induced defects, all test chips underwent thermal displacement-induced fatigue in a temperature range of −65°C to 150°C within a 30 minute time period, as shown in Fig. 4. Figure 4 is a graph showing the thermal-cycling profile.6) After test specimens were thermally-cycled up to the predetermined number (i.e., 200, 400, 600, 800, and 1000 cycles), they were decapsulated for in-situ examination. In order to more precisely investigate and characterize the Si3N4 damage aspect in the scribe region, all test devices were inspected under an optical microscope (OM) and scanning electron microscope (SEM). The edge portion of each test device was first inspected under an optical microscope (OM), and then the corresponding device was precisely examined under a scanning electron microscope (SEM).
Schematics illustrating cross-sectional views of silicon wafers with three different types of passivation coverage in scribe regions; a) not covered, b) half-covered, and c) fully covered.
Schematic illustrating sawing process.
Schematic showing cross-sectional view of LOC package.
Graph showing temperature change profile.
The present experimental results show that the existence of passivated dummy patterns (i.e., TEG patterns) in the scribe regions of semiconductor wafers can be a critical factor in determining the reliability of devices that are individually diced from a wafer by mechanical sawing. Figure 5 is a graph showing the degree of sawing-induced pattern damage as a function of the revolving velocity of a saw blade for 3 different Si3N4 coverage types in the scribe regions. Herein, the A-type indicates that the Si3N4 layer is completely removed in the entire scribe region. The B-type shows that only half of the scribe region (i.e., the outside half of the scribe region with respect to the center line) is covered by the Si3N4 layer. And, the C-type indicates that the entire scribe region is fully covered by the Si3N4 layer. Since the Si3N4 layer is generally the most fragile material in the semiconductor device pattern, the magnitude of the pattern damage is mainly determined by the severity of the Si3N4 damage. So, this work focused on the measurement of the largest Si3N4 damage magnitude to estimate device reliability at a given condition. Since the magnitude of the largest Si3N4 damage (L) is strongly influenced by the width of the scribe region (W), it is expressed as a normalized value (i.e., L/W), as shown in Fig. 5. The present experimental results show that the magnitude of Si3N4 damage increases with increasing sawing velocity. This result also shows that the magnitude of the Si3N4 damage is strongly affected by modifying of the pattern design in the scribe region, in addition to the revolving velocity of the saw blade. Figure 5 shows that the magnitude of the Si3N4 damage is larger by 43% in devices with C-type patterns than in those with A-type patterns at a sawing velocity of 50000 rpm.
Graph showing normalized size of largest passivation damage as a function of sawing velocity and passivation covering pattern in scribe region.
Figure 6 is a micrograph showing the severe Si3N4 damage on the device with the C-type pattern separated at a sawing velocity of 50000 rpm. This in-situ examination indicates that the Si3N4 damage in the active region as well as the scribe region can be considerably influenced by the magnitude of the Si3N4-covering area in the scribe region. That is, the cracks in the Si3N4 layer with the C-type coverage pattern propagate up to a location in the active region, beyond the chipping damage scope. This implies that sawing-driven Si3N4 damage takes place under a mechanism different from that of chipping damage. As detailed in the discussion, it is thought that Si3N4 damage in the scribe region results from brittle fracture under plane stress condition in the final stage of wafer separation, while chipping damage is more influenced by cleavage fracture along a particular crystal plane of the silicon wafer. As a result, Si3N4 damage can occur more randomly and more broadly than chipping damage does. This may be the reason why the magnitude of the Si3N4 damage is much larger for the devices with C-type coverage than for those with A-type or B-type coverage, as shown in Fig. 5. Figure 7 shows the chipping damage in a device with A-type coverage at an intermediate sawing velocity of 50000 rpm. This micrograph proves that the Si3N4 layer in the active region has no damage, even up to the sawing velocity of 50000 rpm in the devices with A-type coverage. This microscopic examination proves that the scribe region with A-type coverage undergoes only chipping-induced damage at a sawing velocity lower than 50000 rpm. The reason why the active device region is safe at a sawing velocity lower than 50000 rpm is that chipping damage occurs without any Si3N4 damage within the scribe region with A-type coverage. However, at a sawing velocity faster than 60000 rpm, the Si3N4 layer in the active region beyond the scribe region was not safe. This is detailed in the discussion.
Optical micrograph showing passivation damage in a scribe region fully-covered by a passivation layer under sawing velocity of 50000 rpm.
Micrograph showing chipping damage in scribe region uncovered by passivation layer under sawing velocity of 50000 rpm.
Meanwhile, in cases of B or C-type coverage, diced devices with sawing-driven Si3N4 damage in the scribe region were potentially exposed to serious reliability problems because damage could propagate into the active region during a reliability test, such as a test of thermal-cycling. That is, the Si3N4 layer itself is very fragile, and so it can be a very effective carrier to transfer the sawing-induced damage in the scribe region to the active region during thermal-cycling. Figure 8 is a 3-dimentional graph showing the normalized value of the largest Si3N4 damage magnitude, as a function of the revolving velocity of a saw blade and the number of thermal cycles for devices with C-type Si3N4 coverage, measured for a diced device. We can see from this graph that the Si3N4 damage magnitude can increase with increasing thermal cycles as well as sawing velocity. This result implies that during thermal-cycling sawing-induced Si3N4 damage can grow due to thermal displacement mismatch between the silicon substrate and its over-covered packaging materials. Indeed, it has already been reported that during the cooling portion of thermal-cycling Si3N4 damage can propagate in order to accommodate the thermal shrinkage of a ductile packaging material such as adhesive in a lead-on-chip package.12) Particularly, a previous article indicated that Si3N4 damage nucleated at the edge of a device can propagate inside the device because thermal displacement mismatch-induced shear stress is much larger at the device edge than at the device center during thermal-cycling.13) This explains the reason why Si3N4 damage that initiated in the scribe region corresponding to the chip edge increases, probably toward the device center, with thermal-cycling.
Three-dimensional graph showing normalized value of largest passivation damage size as a function of revolving velocity of a blade and number of thermal cycles (for C-type specimens).
Figure 9 is another 3-dimentional graph showing the normalized value of the largest Si3N4 damage magnitude measured in the active region as a function of the revolving velocity of a saw blade and the number of thermal cycles for diced devices with A-type Si3N4 coverage. According to these results, the magnitude of Si3N4 damage measured in the active region was negligible at a sawing velocity lower than 50000 rpm, but increased meaningfully with increasing thermal-cycling at a sawing velocity of 60000 rpm. This result proves that once the chipping-driven Si3N4 damage initiates in the active region during wafer separation at a sawing velocity of 60000 rpm, it can grow inside the active region with thermal-cycling. So, if sawing-induced Si3N4 damage exists at any edge of the active region, the device will never be safe during a reliability test such as thermal-cycling, regardless of the pattern type in the scribe region. Consequently, in order to prevent device reliability degradation during thermal-cycling, the sawing process should be performed at a revolving velocity lower than 50000 rpm; as well Si3N4-free coverage must be adopted in the scribe region.
Three-dimensional graph showing normalized value of largest passivation damage size as a function of sawing speed and thermal cycle (for A-type specimens).
It has been reported that the final stage of silicon wafer separation usually takes place by brittle-fracture instead of pure sawing-induced separation because it occurs before a saw blade completely penetrates into the wafer.6) Figure 10 is a schematic providing a cross-sectional view of the silicon wafer with a C-type Si3N4 layer in its scribe region. This drawing explains that as the saw blade penetrates up to an area near the bottom surface of the wafer for final separation, the surface with the scribe region covered by the Si3N4 layer can finally be separated by other mechanical actions instead of sawing-driven friction. Herein, the ultra-thin Si3N4 layer, which is the most fragile part of the device pattern, can be subjected to biaxial tensile stress much larger than the last portion of the silicon wafer can endure. Figure 10 shows that the Si3N4 layer has a thickness much smaller than that of the last silicon layer, which will ultimately be separated. Furthermore, to ensure non-conductivity and corrosion protection, the Si3N4 layer has a non-crystal structure, and so its fracture direction is not sensitive to the crystallographic orientation at all. Meanwhile, silicon has a single crystal structure that can be fractured more favorably along a particular direction.7–11) Thus, the ultra-thin Si3N4 layer can crack more severely and more randomly to accommodate much larger sawing-driven biaxial tensile stress applied to it prior to the ultimate fracture of the silicon. Moreover, since Si3N4 layers generally have poor adhesion strength with silicon, they can be easily separated from the silicon surface during the final sawing-driven loading. After the Si3N4 layer fracture, the last portion of the silicon wafer can be subsequently fractured to accommodate the last sawing-induced impact. Since the fracture in the last layer of silicon has a tendency to preferentially occur along a particular crystal plane (i.e., cleavage crystal plane) parallel to the saw blade forwarding direction, the chipping damage should occur within a scope more limited than that of Si3N4 layer damage. That is, since the predetermined dicing direction is one of ⟨001⟩-crystal directions and the dicing plane should be one of {110}-cleavage planes, the last silicon layer can be preferentially fractured along a (110)-plane parallel to the [001]-sawing direction. As a result, as long as the sawing blade revolving velocity is not too high, the damage of the last silicon layer can remain within the scribe region.
Schematic illustrating cross-sectional view of silicon wafer covered by a passivation layer.
Meanwhile, Fig. 11 shows a cross-sectional view of a silicon wafer with Si3N4-excluded scribe region (i.e., A-type coverage). This schematic illustrates that as a saw blade penetrates up to near the Si3N4-free bottom surface of the last silicon layer for final separation, sawing-induced biaxial tensile stress can be directly applied to the bottom surface of the bare silicon. So, the last silicon layer can be separated without any Si3N4 damage in the scribe region. In this case, as long as the chipping damage stays within the scribe region, there exists no chance to degrade the reliability of the active pattern. However, it has been reported that the cleavage fracture of the last silicon layer along the predetermined dicing direction can be influenced by the rapid revolving velocity of the saw blade.11) That is, rapid sawing-induced impact energy may change the direction of silicon fracture. So, under rapid sawing velocity, the fracture of the last silicon layer may occur beyond the scribe region, even in a location that corresponds to the inside of the active region. This may be the reason why the device with A-type coverage in its scribe region has Si3N4 damage at the sawing velocity of 60000 rpm. That is, depending on the sawing velocity, there seems to be a transition between cleavage fracture and non-cleavage fracture in the last silicon layer. If the sawing velocity is lower than a transition value, the last silicon layer is mainly separated by cleavage fracture, and so the resulting chipping damage can stay mostly within the scribe region. The device with A-type coverage is much safer than that with C-type coverage. However, if the sawing velocity is higher than the transition value, the last silicon layer may be separated by non-cleavage fracture, resulting in chipping damage beyond the scribe region. In this case, the A-type coverage device and the C-type coverage device, which are separated at a sawing velocity larger than the transition value, may have similar Si3N4 damage magnitude. The device with A-type coverage is not safe anymore, particularly during thermal-cycling. Consequently, non-cleavage fracture in the last silicon layer by an abrupt increase in sawing velocity may degrade device reliability, regardless of the Si3N4 coverage type in the scribe region. Thus, unless the sawing velocity is lower than the transition value, the active regions of devices separated from wafers with Si3N4-free scribe regions will not be reliable.
Schematic showing cross-sectional view of silicon wafer with passivation-excluded scribe region (i.e., A-type pattern).
This work proves that the reliability of an active device pattern is strongly influenced by the pattern design in the scribe region, as well as by wafer sawing velocity. The experimental results show that if the scribe region is fully covered by an Si3N4 layer (i.e., C-type coverage in the scribe region), sawing-induced Si3N4 damage can reach to the active region, beyond the scope of sawing-driven chipping damage, even at sawing velocity lower than 30000 rpm. Meanwhile, the active pattern of devices with Si3N4-free scribe regions (i.e., A-type coverage) are safe, even at sawing velocity of 50000 rpm. This study explains that even when chipping damage occurs within the scribe region, C-type Si3N4 damage can propagate up to the active region because ultra-thin Si3N4 layers can be subjected to biaxial tensile stress much larger than the silicon dose during the last stage of sawing. Ultra-thin Si3N4 layers preferentially and randomly crack due to large sawing-induced biaxial stress, while the last portions of silicon layers finally separate as a result of cleavage fracture along a specific crystallographic direction at low sawing velocity. Particularly, since Si3N4 layers in the scribe region can be carriers to transfer sawing-induced damage to the active region, Si3N4 damage in the scribe region can grow into the active region during thermal-cycling. As a result, the existence or not of the Si3N4 layer in the scribe region is significantly important in the reliability of active patterns. However, this work shows that if the sawing velocity is too rapid (i.e., 60000 rpm in this study), the last portion of the silicon does not separate only as a result of cleavage fracture anymore. The complete elimination of Si3N4 layer in the scribe region is not so effective for the protection of the active pattern under rapid sawing velocity. Consequently, as long as the sawing velocity is maintained under a value of 50000 rpm, the active regions of devices separated from wafers with Si3N4-free scribe regions can be safe.
This work was supported by Incheon National University fund for research year, 2017.
