PERFORMANCE OF SR LITHOGRAPHY IN GIGA-BIT DRAM FABRICATION

抄録

We have studied the characteristics of replicated resist pattern by synchrotron radiation (SR) lithography on the real topographic substrates such as a dynamic random access memory (DRAM) structure. Two type topographic structures; the step height between memory cell area and peripheral circuit area, which is regarded as the deviation of the mask/wafer gap and causes the difference of the optical image at each area, and small topographic structure in the memory cell area where the resist thickness changes continuously. It was found that the critical dimension (CD) was controlled within ±10% CD at the range of the proximity gap 14μm and a high contrast resist is effective to control the CD deviation in the memory cell area. On the real DRAM topographic structure at the height of 500Å, we obtained the CD deviation of 0.014μm(3σ) for 0.14μm transfer gate pattern. These results show SR lithography is the promising technique for giga bit scale device fabrication.