Accelerating Extended Hamming Code Decoders on Graphic Processing Units for High Speed Communication

抄録

Emerging networks characterized by growing speed and data insensitivity demand faster and scalable error handling. Prevalent decoders are based on dedicated hardware, offering considerable processing speed, but limited flexibility, programmability and scalability. This paper proposes an efficient approach to accelerate the extended-Hamming code decoder using a graphics processing unit (GPU), chosen for its low cost and extremely high-throughput parallel-computing capability. This paper compares the performance of the GPU-based approach with the equivalent sequential approaches that are performed on a central processing unit (CPU) and Texas Instruments TMS320C6742 digital signal processor (DSP) with varying packet sizes and error tolerances. Experimental results demonstrate that the proposed GPU-based approach outperforms the sequential approaches in terms of execution time and energy consumption.