2017 Volume E100.C Issue 3 Pages 329-339
A comprehensive model is presented for estimating the bit error rate (BER) of write disturbance in a resistive memory composed of a cross-point array. While writing a datum into the selected address, the non-selected addresses are biased by word-line (WL) and bit-line (BL). The stored datum in the non-selected addresses will be disturbed if the bias is large enough. It is necessary for the current flowing through the non-selected address to be calculated in order to estimate the BER of the write disturbance. Since it takes a long time to calculate the current flowing in a large-scale cross-point array, several simplified circuits have been utilized to decrease the calculating time. However, these simplified circuits are available to the selected address, not to the non-selected one. In this paper, new simplified circuits are proposed for calculating the current flowing through the non-selected address. The proposed and the conventional simplified circuits are used, and on that basis the trade-off between the write disturbance and the write error is discussed. Furthermore, the error correcting code (ECC) is introduced to improve the trade-off and to provide the low-cost memory chip matching current production lines.
