In this study, we investigated Si(100), Si(110) and Si(111) surface flattening process utilizing sacrificial oxidation method, and its effect on Metal-Insulator-Semiconductor (MIS) diode characteristics. By the etching of the 100 nm-thick sacrificial oxide formed by thermal oxidation at 1100°C, the surface roughness of Si(100), Si(110) and Si(111) substrates were reduced. The obtained Root-Mean-Square (RMS) roughness of Si(100) was reduced from 0.22 nm (as-cleaned) to 0.07 nm (after etching), while it was reduced from 0.23 nm to 0.12 nm in the case of Si(110), and from 0.23 nm to 0.11 nm in the case of Si(111), respectively. Furthermore, it was found that time-dependent dielectric breakdown (TDDB) characteristics of MIS diodes for p-Si(100), p-Si(110) and p-Si(111) were improved with the reduction of Si surface RMS roughness.
We have investigated PtHf silicide formation utilizing a developed PtHf-alloy target to realize low contact resistivity for the first time. A 20 nm-thick PtHf-alloy thin film was deposited on the n-Si(100) by RF magnetron sputtering at room temperature. Then, silicidation was carried out by rapid thermal annealing (RTA) system at 450-600°C/5 min in N2/4.9%H2 ambient. The PtHf-alloy silcide, PtHfSi, layers were successfully formed, and the Schottky barrier height (SBH) for electron of 0.45 eV was obtained by 450°C silicidation. Furthermore, low contact resistivity was achieved for fabricated PtHSi such as 8.4x10-8 Ωcm2 evaluated by cross-bridge Kelvin resistor (CBKR) method.
An application of laser annealing process, which is used to form the P-type Base junction for high-performance low-voltage power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), is proposed. An equivalent shallow-junction structure for P-Base junction with uniform impurity distribution is achieved by adopting green laser annealing of pulsed mode. Higher impurity activation for the shallow junction has been achieved by the laser annealing of melted phase than by conventional RTA (Rapid Thermal Annealing) of solid phase. The application of the laser annealing technology in the fabrication process of Low-Voltage U-MOSFET is also examined.
This paper investigates current-gain and high-frequency characteristics of double heterojunction bipolar transistors (DHBTs) with a uniform GaAsSb, compositionally graded GaAsSb, uniform InGaAsSb, or compositionally graded InGaAsSb base. DHBTs with a compositionally graded InGaAsSb base exhibit a high current gain of ∼75 and fT=504GHz. In order to boost fmax of DHBTs with a compositionally graded InGaAsSb base, a highly doped GaAsSb base contact layer is inserted. The fabricated DHBTs exhibit fT/fmax=513/637GHz and a breakdown voltage of 5.2V.
We developed a 300-GHz high gain amplifier MMIC in 75-nm InP high electron mobility transistor technology. We approached the issues with accurate characterization of devices to design the amplifier. The on-wafer through-reflect-line calibration technique was used to obtain accurate transistor characteristics. To increase measurement accuracy, a highly isolated structure was used for on-wafer calibration standards. The common source amplifier topology was used for achieving high gain amplification. The implemented amplifier MMIC exhibited a gain of over 25 dB in the 280-310-GHz frequency band.
In this research, we have investigated the deposition condition of pentacene film on nitrogen doped (N-doped) LaB6 donor layer for larger grain growth at the channel region for bottom-contact type pentacene-based organic field-effect transistors (OFETs) to improve the device characteristics. Source and drain bottom-contacts of Al were patterned and 2nm-thick N-doped LaB6 donor layer was deposited on the SiO2/Si(100) back-gate structure. The dendritic grain growth of pentacene larger than 10µm without lamellar grain growth was demonstrated when the deposition temperature and rate were 100°C and 0.5nm/min, respectively. Furthermore, it was found that the dendritic grain growth was realized at the boundary region of bottom-contact as well as channel region.
To find the optimal design in alleviating the effect of random variations on a SRAM cell, a worst-case sampling method is used. From the quantitative analysis using this method, the optimal designs for a process-variation-tolerant 22-nm FinFET-based 6-T SRAM cell are proposed and implemented through cell layouts and a dual-threshold-voltage designs.
A negative capacitor is fabricated using poly(vinylidene fluoride-trifluoroethylene) copolymer and connected in series to an a-IZO TFT. It is experimentally demonstrated that the negative capacitance of the negative capacitor can create steep switching in the a-IZO TFT (e.g., a subthreshold slope change from 342mV/decade to 102mV/decade at room-temperature).
In this work, the bias polarity dependent resistive switching behaviors in Cu/Si3N4/p+ Si RRAM memory cell have been closely studied. Different switching characteristics in both unipolar and bipolar modes after the positive forming are investigated. The bipolar switching did not need a forming process and showed better characteristics including endurance cycling, uniformity of switching parameters, and on/off resistance ratio. Also, the resistive switching characteristics by both positive and negative forming switching are compared. It has been confirmed that both unipolar and bipolar modes after the negative forming exhibits inferior resistive switching performances due to high forming voltage and current.
We fabricated bulk heterojunction organic solar cells based on 1,2-dichlorobenzene solutions of poly[[4,8-bis[(2-ethylhexyl) oxy]benzo[1,2-b:4,5-b'] dithiophene-2,6-diyl] [3-fluoro-2-[(2-ethylhexyl) carbonyl]thieno [3,4-b]-thiophenediyl]] (PTB7): [6,6]-phenyl-C71-butyric-acid-methyl-ester (PTB7:PC71BM) with additional dimethyl sulfoxide (DMSO) and surfactants diiodooctane (DIO). The optimal weight ratios of DMSO and DIO relative to the total weight of PTB7:PC71BM were 13% and 3%, respectively, and the resulting solar cells exhibited an open circuit voltage of 0.72 V, short circuit current density of 15.63 mA/cm2, fill factor of 0.49, and power conversion efficiency of 5.47%. The surfaces of the active layers deposited with added DMSO and DIO were smoother than those of the layers without the added surfactants and consisted of smaller nanograins, which may have resulted in the improved solar cell performance.
Organic solar cells are expected to have superior performance in terms of flexibility and low-cost fabrication. However, conventional organic solar cells usually have issues while using rare earth ITO materials and have poor long-term reliability. To seek possible solutions for these issues, we fabricated an inverted solar cell structure of PEN/PEDOT:PSS/PFN/PTB7:PC71BM/MoO3/Au, and found that the fabricated devices had considerably improved long-term reliability when stored in air without any surface passivation layer. The resultant conversion efficiency of the solar cell was 1.88%, and it decreased to 90% of its initial value after 100 h of storage in air.
Effects of electron beam irradiation at 15 keV on graphene are investigated by optical and electron characterization using Raman and two-terminal resistance measurement and photoconductivity measurement. In Raman spectra, increase of defects in D-peak to G-peak ratio by increase of electron irradiation by 70 mC/cm2 was found. Resistance of graphene showed an increase after the irradiation. Rather sensitive change was found in photoconductivity of irradiated graphene under ultra-violet (UV) illumination, suggesting irradiation induced defects affect a photoconductivity properties of the graphene.
Radio over Fiber (RoF) is a promising solution for providing wireless access services. Heterogeneous radio signals are transferred via an optical fiber link using an analog transmission technique. When the RoF and the radio frequency (RF) devices have a nonlinear characteristic, these will create the intermodulation products (IMPs) in the system and generate the intermodulation distortion (IMD). In this paper, the IMD interference in the uplink RF signals from the coupling effect between the downlink and the uplink antennas has been addressed. We propose a method using the dynamic channel allocation (DCA) algorithm with the predistortion (PD) technique to improve the throughput performance of the multi-channel RoF system. The carrier to distortion plus noise power ratio (CDNR) is evaluated for all channel allocation combinations; then the best channel combination is assigned as a set of active channels to minimize the effect of IMD. The results show that the DCA with PD has the lowest IMD and obtains a better throughput performance.
We propose a low-noise and low-power dynamic comparator with an offset calibration circuit for Low-Power ADCs. The proposed comparator equips the control circuit in order to switching the comparison accuracy and the current consumption. When high accuracy is not required, current consumption is reduced by allowing the noise increase. Compared with a traditional dynamic comparator, the proposed architecture reduced the current consumption to 78% at 100MHz operating and 1.8V supply voltage. Furthermore, the offset voltage is corrected with minimal current consumption by controlling the on/off operation of the offset calibration circuit.
This study proposes the application and implementation of a new power factor correction (PFC) with a variable slope ramp for a small wind power system without any input voltage sensing circuits or external control components in the current shaping loop. The hardware description of the variable slope ramp simplifies the complexity of integrated circuit realization with low resolution analog-to-digital converters, and achieves a high power factor for multi and three-phase AC/DC converters such as wind power systems. Up to 1 kW small wind power system is tested to verify the performance of the proposed PFC control. The highest achieved power factor reaches 99.5%.
Layout strategies including source edge to substrate space (SESS) and inserted substrate-pick stripes of gate-grounded NMOS(ggNMOS) are optimized in this work for on-chip electrostatic discharge (ESD) protection. In order to fully investigate influences of substrate resistors on triggering and conduction behaviors of ggNMOS, various devices are designed and fabricated in a 65-nm CMOS process. Direct current (DC), transmission-line-pulsing (TLP), human body model (HBM) and very-fast TLP (VF-TLP) tests are executed to fully characterize performance of fabricated ggNMOS. Test results reveal that an enlarged SESS parameter results in an earlier triggering behavior of ggNMOS, which presents a layout option for subtle adjustable triggering behaviors. Besides, inserted substrate-pick stripes are proved to have a bell-shape influence on the ESD robustness of ggNMOS and this bell-shape influence is valid in TLP, HBM and VF-TLP tests. Moreover, the most ESD-robust ggNMOS optimized under different inserted substrate-pick stripes always achieves a higher HBM level over the traditional ggNMOS at each concerned total device-width. Physical mechanisms of test results will be deeply discussed in this work.
This paper proposes a high clutter-rejection technique for wall-penetrating frequency-modulated continuous-wave (FMCW) radar. FMCW radars are widely used, as they moderate the receiver saturation problem in wall-penetrating applications by attenuating short-range clutter such as wall-clutter. However, conventional FMCW radars require a very high-order high-pass filter (HPF) to attenuate short-range clutter. A delay-line (DL) is exploited to overcome this problem. Time-delay shifts beat frequencies formed by reflection waves. This means that a proper time-delay increases the ratio of target-beat frequency to clutter-beat frequency. Consequently, low-order HPF fully attenuates short-range clutter. A third-order HPF rejects more than 20 dB and 30 dB for clutter located at 6 m and 3 m, respectively, with a target located at 9 m detection with a 10,000 GHz/s chirp rate and a 28 ns delay-line.
An application of laser annealing process, which is used to form the shallow P-type Base junction for 20-V planar power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) is proposed. We demonstrated that the fabricated devices integrated with laser annealing process have superior electrical characteristics than those fabricated according to the standard process. Moreover, the threshold voltage variation of the devices applied by the new annealing process is effectively suppressed. This is due to that a uniform impurity distribution at the channel region is achieved by adopting laser annealing. Laser annealing technology can be applied as a reliable, effective, and advantageous process for the low-voltage power MOSFETs.
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