A 32bit CPU, which can operate more than 15 years with 220mAH Li battery, or eternally operate with an energy harvester of in-door light is presented. The CPU was fabricated by using 65nm SOTB CMOS technology (Silicon on Thin Buried oxide) where gate length is 60nm and BOX layer thickness is 10nm. The threshold voltage was designed to be as low as 0.19V so that the CPU operates at over threshold region, even at lower supply voltages down to 0.22V. Large reverse body bias up to -2.5V can be applied to bodies of SOTB devices without increasing gate induced drain leak current to reduce the sleep current of the CPU. It operated at 14MHz and 0.35V with the lowest energy of 13.4 pJ/cycle. The sleep current of 0.14µA at 0.35V with the body bias voltage of -2.5V was obtained. These characteristics are suitable for such new applications as energy harvesting sensor network systems, and long lasting wearable computers.
RXv2 is the new generation of Renesas's processor architecture for microcontrollers with high-capacity flash memory. An enhanced instruction set and pipeline structure with an advanced fetch unit (AFU) provide an effective balance between power consumption performance and high processing performance. Enhanced instructions such as DSP function and floating point operation and a five-stage dual-issue pipeline synergistically boost the performance of digital signal applications. The RXv2 processor delivers 1.9 - 3.7 the cycle performance of the RXv1 in these applications. The decrease of the number of Flash memory accesses by AFU is a dominant determiner of reducing power consumption. AFU of RXv2 benefits from adopting branch target cache, which has a comparatively smaller area than that of typical cache systems. High code density delivers low power consumption by reducing instruction memory bandwidth. The implementation of RXv2 delivers up to 46% reduction in static code size, up to 30% reduction in dynamic code size relative to RISC architectures. RXv2 reaches 4.0 Coremark per MHz and operates up to 240MHz. The RXv2 processor delivers approximately more than 2.2 - 5.7x the power efficiency of the RXv1. The RXv2 microprocessor achieves the best possible computing performance in various applications such as building automation, medical, motor control, e-metering, and home appliances which lead to the higher memory capacity, frequency and processing performance.
As energy consumption of cache memories increases, an energy-efficient cache management mechanism is required. While a dynamic cache resizing mechanism is one promising approach to the energy reduction of microprocessors, one problem is that its effect is limited by the existence of dead-on-fill blocks, which are not used until their evictions from the cache memory. To solve this problem, this paper proposes a cache management policy named FLEXII, which can reduce the number of dead-on-fill blocks and help dynamic cache resizing mechanisms further reduce the energy consumption of the cache memories.
The authors have been researching on reducing the power consumption of microprocessors, and developed a low-power processor called “Geyser” by applying power gating (PG) function to the individual functional units of the processor. PG function on Geyser reduces the power consumption of functional units by shutting off the power voltage of idle units. However, the energy overhead of switching the supply voltage for units on and off causes power increases. The amount of the energy overhead varies with the behavior of each functional unit which is influenced by running application, and also with the core temperature. It is therefore necessary to switch the PG function itself on or off according to the state of the processor at runtime to reduce power consumption more effectively. In this paper, the authors propose a PG control method to take the power overhead into account by the operating system (OS). In the proposed method, for achieving much power reduction, the OS calculates the power consumption of each functional unit periodically and inhibits the PG function of the unit whose energy overhead is judged too high. The method was implemented in the Linux process scheduler and evaluated. The results show that the average power consumption of the functional units is reduced by up to 17.2%.
Modern processors use Branch Target Buffer (BTB) to relax control dependence. Unfortunately, the energy consumption of the BTB is high. In order to effectively fetch instructions, it is necessary to perform a branch prediction at the fetch stage, regardless of whether the fetched instruction is a branch or a nonbranch. Therefore, the number of accesses to the BTB is large, and the energy consumption of the BTB is high. However, accesses from nonbranches to the BTB waste energy. In this paper, we focus on accesses from nonbranches to the BTB, which we call useless accesses from a viewpoint of power. For reducing energy consumption without performance loss, we present a method that reduces useless accesses by using information that indicates whether a fetched instruction is a branch or not. To realize the above approach, we propose a branch bit called B-Bit. A B-Bit is associated with an instruction and indicates whether it is a branch or not. A B-Bit is available at the beginning of the fetch stage. If a B-Bit is “1” signifying a branch, the BTB is accessed. If a B-Bit is “0” signifying a nonbranch, the BTB is not accessed. The experimental results show that the total energy consumption can be reduced by 54.3% without performance loss.
To eliminate CAMs from the load/store queues, several techniques to detect memory access order violation with hash filters composed of RAMs have been proposed. This paper proposes a technique with parallel counting Bloom filters (PCBF). A Bloom filter has extremely low false positive rates owing to multiple hash functions. Although some existing researches claim the use of Bloom filters, none of them make mention to multiple hash functions. This paper also addresses the problem relevant to the variety of access sizes of load/store instructions. The evaluation results show that our technique, with only 2720-bit Bloom filters, achieves a relative IPC of 99.0% while the area and power consumption are greatly reduced to 14.3% and 22.0% compared to a conventional model with CAMs. The filter is much smaller than usual branch predictors.
This paper presents a new parallel architecture of syndrome generator for a high-speed BCH (Bose-Chaudhuri-Hocquenghem) decoder. In particular, the proposed parallel syndrome generators are based on LFSR (linear feedback shift register) architecture to achieve high throughput without significant area overhead. From the experimental results, the proposed approach achieves 4.60 Gbps using 0.25-µm standard CMOS technology. This result is much faster than the conventional byte-wise GFM-based counterpart. The high throughputs are due to the well-tuned hardware implementation using unfolding transformation.
Special Section on Microwave and Millimeter-Wave Technology
This invited paper aims to present an overview of our recent research and development (R&D) of advanced microwave planar filters, in particular with miniaturization and/or electronically tunable/ reconfigurable functionalities, which are in demand for future communication/radar systems as well as emerging wireless applications.
This work addresses two key topics in the field of energy harvesting and wireless power transfer. The first is the optimum signal design for improved RF-DC conversion efficiency in rectifier circuits by using time varying envelope signals. The second is the design of rectifiers that present reduced sensitivity to input power and output load variations by introducing resistance compression network (RCN) structures.
In 1919 the Department of Electrical Engineering (EE) was established in Tohoku University (at that time, Tohoku Imperial University). In this Department a growing tendency towards research featured in science and technology for electrical communication. Great efforts made in these fields produced pioneering studies such as those of the Yagi-Uda antenna and slotted-anode type magnetrons in the late 1920s. The purpose of this article is to introduce the history of development of microwave electron-tube at Tohoku University, which was started with the Okabe's magnetron.
Invention and development of the Yagi-Uda antenna in Tohoku University, Japan are described. Communication experiments in VHF and UHF frequency bands using transmitter and receiver developed in the same university as well as the Yagi-Uda antenna are also presented. Then, self-complementary antennas, which is the frequency independent antenna invented in Tohoku University are described. Analysis methods of large loop antennas is also presented.
This invited paper is dedicated to introduce recent activities of Japanese microwave industries. 7 topics are introduced from major microwave companies in Japan. All topics are from invited talks in 2014 Asia-Pacific microwave conference (APMC2014) held in Sendai, November, 2014.
This paper presents wireless systems for use in disaster recovery operations. The Great East Japan Earthquake of March 11, 2011 reinforced the importance of communications in, to, and between disaster areas as lifelines. It also revealed that conventional wireless systems used for disaster recovery need to be renovated to cope with technological changes and to provide their services with easier operations. To address this need we have developed new systems, which include a relay wireless system, subscriber wireless systems, business radio systems, and satellite communication systems. They will be chosen and used depending on the situations in disaster areas as well as on the required services.
Current mobile communication terminals are equipped with multiple RF circuits that cover all frequency bands assigned for the communication. In order to make efficient use of frequency spectrum and to reduce circuits in a terminal, a low-loss reconfigurable RF filter is necessary to flexibly change RF frequencies. In this paper, a new reconfigurable bandpass filter (BPF) having eight-frequency (three-bit) selection capability is proposed. It employs branch-line switched type variable resonators that provide low insertion loss. One of the design issues is how to control pass bandwidths among selectable frequencies. In order to analyze the bandwidth variation of the reconfigurable BPF, we calculate the changes of external Q and coupling coefficients. It is shown that the inductive coupling design can achieve less variation of bandwidth for the reconfigurable BPF, compared with commonly used capacitive coupling design. A prototype BPF on a printed circuit board with high dielectric constant substrate has been fabricated and evaluated in 2 GHz bands. It presents performance very close to the design results with respect to insertion loss, center frequency and passband bandwidth. Low insertion loss of less than 1 dB is achieved among the eight frequencies.
A miniaturized patch hybrid coupler with arbitrary power ratio and impedance transformation is proposed and designed by loading a pair of asymmetric cross slots on a squared patch resonator. To obtain the arbitrary power ratio and impedance transformation, the rectangular size of stepped slot ends should be well designed to be asymmetry and thus to obtain the different inductive loadings along two current paths. Theoretically, the equivalent transmission line model is first developed to understand the physical relationship between the patch and traditional branch-line hybrids. The matching/isolation and power ratio conditions are then derived at center frequency. By following a detailed design guideline, a prototype of the hybrid with 1:2 power ratio and 1:1.3 impedance transformation is designed and fabricated at 4.2 GHz. The measured results show a good agreement with simulated results, where the measured -10 dB impedance bandwidth achieves 18% and the bandwidth of 90°±6° phase difference is about 35% in a frequency range from 3.5 GHz to 5 GHz.
This paper presents a novel CMOS bias topology serving as not only a bias circuit but also an adaptive linearizer for SiGe HBT power amplifier (PA) IC. The novel bias circuit can well keep the base-to-emitter voltage (Vbe) of RF amplifying HBT constant and adaptively increase the base current (Ib) with the increase of the input power. Therefore, the gain compression and phase distortion performance of the PA is improved. A three-stage 5-GHz band PA IC with the novel bias circuit for WLAN applications is designed and fabricated in IBM 0.35µm SiGe BiCMOS technology. Under 54Mbps OFDM signal at 5.4GHz, the PA IC exhibits a measured small-signal gain of 29dB, an EVM of 0.9% at 17dBm output power and a DC current consumption of 284mA.
Novel multi-band mixers that can receive multiple band signals concurrently are proposed and evaluated. The mixers achieve independent gain control through novel relative power control method of the multiple local oscillator (LO) signals. Linear control is also achieved through multiple LO signal input with total LO power control. Theoretical analysis shows that odd-order nonlinearity components of the multiple LO signals support linear conversion gain control. Dual- and triple-band tests are conducted using typical three MOSFET mixers fabricated by a 0.25 µm SiGe BiCMOS process. Measurements confirm over 40 dB independent control of conversion gain, linear control achieved through LO input power control. The proposed mixers have high input linearity with a 5 dBm output third intercept point. A method is also proposed to reduce interference caused by mixing between multiple LO signals.
RF under sampling is more suitable for Satellite receiver systems in comparison to terrestrial systems. In conventional RF under sampling the minimum sampling frequency (fs) should be atleast twice the system bandwidth; therefore for a system with a wide bandwidth, a relatively high fs is necessary. In this paper we propose a direct RF under sampling reception method that halves fs. The proposed f's is achieved by folding in band noise in half. A method of adapting f's for the reception of signals in different channels is also proposed; this ensures that the SNR is not degraded for any channel. To evaluate the proposed technique's performance and compare it to the conventional case a 3 channel, 1 GHz band test receiver and it's key device (i.e. S/H circuit) are developed. Using SNR and EVM as performance indexes, the performance of the proposed technique has been evaluated and compared to that of the conventional technique. The evaluation results show that the proposed technique can achieve the same performance as conventional RF under sampling for all 3 channels, using only half of the sampling frequency of the conventional technique.
An adaptively phase-shift controlled self-injection locked VCO is described. A self-injection locking technique is effective to reduce phase noise. However, a conventional self-injection locked VCO has drawbacks of discontinuous frequency sweep which means narrow bandwidth, and large variation of phase noise. Our proposed adaptively phase-shift controlled self-injection locked VCO overcomes these drawbacks by detecting phase-shift of the self-injection feedback and controlling the phase-shift depending on sweep of the oscillation frequency. This paper describes analysis of relationships between the discontinuity and feedback phase-shift of the self-injection locked VCO. In addition, a VCO-IC which includes a Ka-band VCO and a phase detector is designed and fabricated in 0.18um SiGe BiCMOS technology. Measurement results of the proposed self-injection locked VCO using the fabricated IC show the improvement to the drawbacks. In the proposed self-injection locked VCO, the oscillation frequency sweep is continuous and the phase noise variation is less than 5 dB.
In this paper, a 97-mW 8-phase CMOS voltage-controlled oscillator (VCO) and dividers covering the entire VCO oscillation range for a 134-GHz phase-locked loop (PLL) synthesizer are presented. The dividers have two injection-locked frequency dividers (ILFDs), one with and one without an inductor, and a pulse-swallowing counter with a differential dual-modulus prescaler. The VCO has a fundamental oscillation frequency range of 131.8 GHz to 134.3 GHz, achieved by controlling the back-gate voltage, which is also used to tune the locking range of divide-by-2 and divide-by-3 dividers. The ratio between the measured VCO oscillation frequencies and output frequencies of dividers is in good agreement with the target ratio. This indicates that the dividers covered the entire VCO oscillation range. We fabricated the VCO and dividers with a chip core area of 180 µm × 100 µm implemented in a 65-nm CMOS process. The total power consumption was 97 mW at a 1.2-V supply voltage.
In order to efficiently drive a low-power DC motor using microwave power transfer (MPT), a compact power-receiving device is developed, which consists of a rectenna array and an improved DC-DC converter with constant input resistance characteristics. Since the conversion efficiency of the rectenna is strongly affected by the output load, it is difficult to efficiently drive a dynamic load resistance device such as DC motor. Using both continuous-wave (CW) and pulsed-wave MPT, experiments are carried out on driving the DC motor whose load resistance is varying from 36 to 140 Ω. In the CW case, the measured overall efficiency of the power-receiving device is constant over 50% for the power density of 0.25 to 2.08 mW/cm2. In particular, the overall efficiency is 62%, 70.8% for the power density of 0.25, 0.98 mW/cm2 where the received power of the single antenna is 13, 50 mW, respectively. In the pulsed-wave case, the measured overall efficiency is over 44% for a duty ratio of 0.2 to 1 for the power density of 0.98 mW/cm2.
Vertical- and horizontal-polarization RCS of a dipole antenna was reduced using a switchable reflector. The switchable reflector can switch reflection level for the vertical-polarization and have absorption for the horizontal-polarization. The reflection level of the reflector for the vertical-polarization can be switched using pin diodes and the reflection for the horizontal-polarization can be reduced using resistor on the surface. The switchable reflector was designed to operate at 9 GHz and fabricated. The vertical-polarized reflection coefficient was switched -28 dB with OFF-state diodes and -0.7 dB with ON-state diodes, and horizontal-polarized one was less than -18 dB at 9 GHz. The reflector with ON-state diodes was applied to an antenna reflector of a dipole antenna and comparable radiation pattern to that with a metal reflector was obtained at 9 GHz. Moreover the reflector with OFF-state diodes was applied to the reflector of the dipole antenna and the RCS of the dipole antenna was reduced 18 dB for the vertical-polarization and 16 dB for the horizontal-polarization. Therefore the designed switchable reflector can contribute to antenna RCS reduction for dual-polarization at the operating frequency without degrading antenna performance.
A digital spatial modulation method has been demonstrated for a wireless power transmission system at 5.8 GHz. Interference of electromagnetic waves, which are radiated from the dual scatterers, successfully realizes the spatial modulation. The spatial modulation is performed with a digital modulation manner by controlling capacitances embedded in one of the dual scatterers so that the interference of the scattered waves is appropriately changed. Switch MMICs based on p-HEMT technology was newly developed for the spatial modulation. Measured insertion losses of the switch MMIC are 1.0 dB and 14 dB for on and off states at 5.8 GHz, respectively. The isolation is more than 20 dB. With the switch MMIC, digital spatial modulation characteristics were experimentally demonstrated at 5.8 GHz. One-bit amplitude shift keying (ASK) for 1 MHz signal was realized at 5.8 GHz, and two levels were clearly discriminated. The modulation factor is 36%. In addition, 2-bit ASK signal was detected at 7.1 GHz.
This paper describes circuit design and measurement results of a newly proposed GaAs-HBT step-gain amplifier configuration and its application to a 3.3-3.6 GHz WiMAX power amplifier module for use in customer premises equipment. The step-gain amplifier implemented using only a usual HBT process is based on a current-mirror-based, base-collector diode switches and a passive attenuator core for the purpose of bypassing a power-gain stage. The stage allows an individual design approach in terms of gain and attenuation levels as well as large operating current reduction in the attenuation state. To confirm the effectiveness of the proposed step-gain amplifier, a prototype of the amplifier was designed and fabricated, and then a WiMAX power amplifier module was also designed and fabricated as an application example of the proposed configuration to an amplifier product. Measurements are as follows. For a 3.5-V power supply and a 3.5-GHz non-modulated signal, the step-gain amplifier delivers 23.7 dBm of 1-dB gain compressed output power and 10.7 dB of linear gain in the amplification state. In the attenuation state, the amplifier exhibits 21 dBm of 1-dB gain expanded input power, -9.7 dB of gain, and 15 mA of current dissipation while keeping the gain stage switched off and maintaining input and output return loss of less than -10 dB at a 3.5-GHz band. The WiMAX amplifier operating with a 5-V supply voltage and a 64-QAM modulated signal is capable of delivering a 28.5-dBm linear output power, a 37-39 dB gain, and 15% of PAE over a wide frequency range from 3.3 to 3.6 GHz in the high-gain state while keeping error vector magnitude as low as 2.5%. This amplifier, which incorporates the proposed step-gain configuration into its interstage, enables a 24-dB gain reduction and a 45-mA large quiescent current reduction in the low-gain state.
PD-SOI (Partial Depleted Silicon On Insulator) process is a good candidate technology for space system designs, since it features excellent insulation to the silicon substrate compared to the conventional bulk CMOS process. However, the radioactive particles from the low earth orbit can causes single event transient (SET) or abrupt charge collection in a circuit node, leading to a logical error in space systems. Also, the side effects such as the history effect and the kink effect in PD-SOI technology cause the threshold voltage variation, degrading the circuit performance. We propose SET-tolerant PD-SOI CMOS logic circuits using a novel active body-bias scheme. Simulation results show that the proposed circuits are more effective to SET and the side effects as well.
This paper demonstrates the resonant power supply noise reduction effects of STO thin film decoupling capacitors, which are embedded in interposers. The on-interposer STO capacitor consists of SrTiO2 whose dielectric constant is about 20 and is sandwitched by Cu films in an interposer. The on-interposer STO capacitors are directly connected to the LSI PADs so that they provide large decoupling capacitance without package leadframe/bonding wire inductance, resulting in the reduction of the resonant power supply noise. The measured power supply waveforms show significant reduction of the power supply noise, and the Shmoo plots also show the contribution of the STO capacitors to the robust operations of LSIs.
Time redundancy is sometimes an only option for enhancing circuit reliability when the circuit area is severely restricted. In this paper, a time-redundant error-correction scheme, which is particularly suitable for coarse-grained reconfigurable arrays (CGRAs), is proposed. It judges the correctness of the executions by comparing the results of two identical runs. Once a mismatch is found, the second run is terminated immediately to start the third run, under the assumption that the errors tend to persist in many applications, for selecting the correct result in the three runs. The circuit area and reliability of the proposed method is compared with a straightforward implementation of time-redundancy and a selective triple modular redundancy (TMR). A case study on a CGRA revealed that the area of the proposed method is 1% larger than that of the implementation for the selective TMR. The study also shows the proposed scheme is up to 2.6x more reliable than the full-TMR when the persistent error is predominant.