nMOS-type and pMOS-type silicon avalanche photodiodes (APDs) were fabricated by standard 0.18µm CMOS process, and the current-voltage characteristic and the frequency response of the APDs with and without guard ring structure were measured. The role of the guard ring is cancellation of photo-generated carriers in a deep layer and a substrate. The bandwidth of the APD is enhanced with the guard ring structure at a sacrifice of the responsivity. Based on comparison of nMOS-type and pMOS-type APDs, the nMOS-type APD is more suitable for high-speed operation. The bandwidth is enhanced with decreasing the spacing of interdigital electrodes due to decreased carrier transit time and with decreasing the detection area and the PAD size for RF probing due to decreased device capacitance. The maximum bandwidth was achieved with the avalanche gain of about 10. Finally, we fabricated a nMOS-type APD with the electrode spacing of 0.84µm, the detection area of 10×10µm2, the PAD size for RF probing of 30×30µm2, and with the guard ring structure. The maximum bandwidth of 8.4GHz was achieved along with the gain-bandwidth product of 280GHz.
We have derived the physics-based equivalent circuit model of a semiconductor-integrated bow-tie antenna (BTA) for expressing its impedance and radiation characteristics as a terahertz transmitter. The equivalent circuit branches and components, consisting of 16 RLC parameters are determined based on electromagnetic simulations. All the values of the circuit elements are identified using the particle swarm optimization (PSO) that is one of the modern multi-purpose optimization methods. Moreover, each element value can also be explained by the structure of the semiconductor-integrated BTA, the device size, and the material parameters.
In this paper, a novel slow-wave half mode substrate integrated waveguide (SW-HMSIW) structure is presented and experimentally demonstrated, and some interesting slow-wave propagation effects are obtained. The SW-HMSIW enables the cutoff frequency reduction and phase velocity to decrease without sacrificing its performance at the same lateral dimension, which equivalently reduces the lateral dimension and longitudinal size at the same frequency. Specifically, with the different loading microstrip width, a cutoff frequency reduction of 16%, 25%, 30% is achieved compared to the conventional HMSIW at the same lateral dimension. Both lateral and longitudinal size reductions significantly extend the operating range of SIW structures to low frequency region.
This paper proposes a multiway power divider for wideband (4:1) beamforming arrays. The divider's input reflection characteristic (S11) is achieved using a multisection stepped-impedance transformer. Moreover, the divider's isolation (S32) bandwidth is increased by incorporating inductors and capacitors in addition to the conventional resistor only isolation networks of the divider. The analysis of the proposed divider and comparison with the previous research model was conducted with four-way configuration. A prototype of a wideband eight-way power divider is fabricated and measured. The measured fractional bandwidth is about 137% from 1.3 to 6.8GHz with the -10dB criteria of input reflection (S11), output reflection (S22) and isolation (S32) simultaneously.
This paper proposes a low power single-ended successive approximation register (SAR) analog-to-digital converter (ADC) to replace the only analog active circuit, the comparator, with a digital circuit, which is an inverter-based comparator. The replacement helps possible design automation. The inverter threshold voltage variation impact is minimal because an SAR ADC has only one comparator, and many applications are either insensitive to the resulting ADC offset or easily corrected digitally. The proposed resetting approach mitigates leakage when the input is close to the threshold voltage. As an intrinsic headroom-free, and thus low-rail-voltage, friendly structure, an inverter-based comparator also occupies a small area. Furthermore, an 11-bit ADC was designed and manufactured through a 0.35-µm CMOS process by adopting a low-power switching procedure. The ADC achieves an FOM of 181fJ/Conv.-step at a 25kS/s sampling rate when the supply voltage VDD is 1.2V.
This paper presents a low power millimeter-wave oscillator consisting of a current-reused topology and buffer-feedback. By connecting a buffer-feedback topology between the core LC-tank of the oscillator and the output buffer stage, the simulated oscillation frequency of the proposed oscillator is increased by 17%, compared to that of the conventional current-reused oscillator. In addition, to obtain the same output power, the proposed oscillator reduces the power dissipation by 47%, compared to that of the conventional buffer-feedback oscillator. The prototype of the proposed oscillator is fabricated in a 65nm CMOS technology with a size of 700µm×480µm including pad. Measurement results indicate an oscillation frequency of 71.3GHz, while dissipating 10mA from a 1.6V supply.