This paper presents work on integrating wireless 3-D interconnection interface, namely ThruChip Interface (TCI), in three-dimensional field-programmable gate array (3-D FPGA) exploration tool (TPR). TCI is an emerging 3-D IC integration solution because of its advantages over cost, flexibility, reliability, comparable performance, and energy dissipation in comparison to through-silicon-via (TSV). Since the communication bandwidth of TCI is much higher than FPGA internal logic signals, in order to fully utilize its bandwidth, the time-division multiplexing (TDM) scheme is adopted. The experimental results show 25% on average and 58% at maximum path delay reduction over 2-D FPGA when five layers are used in TCI based 3-D FPGA architecture. Although the performance of TCI based 3-D FPGA architecture is 8% below that of TSV based 3-D FPGA on average, TCI based architecture can reduce active area consumed by vertical communication channels by 42% on average in comparison to TSV based architecture and hence leads to better delay and area product.
We measure neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65-nm bulk CMOS process in order to evaluate dependence of MCUs on cell distance and well-contact density using four different shift registers. Measurement results by accelerated tests show that MCU/SEU is up to 23.4% and it is exponentially decreased by the distance between latches on FFs. MCU rates can be drastically reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting well-contact arrays under power and ground rails.
A 60-GHz CMOS transmitter with on-chip antenna for high-speed short-range wireless interconnections is presented. The radiation gain of the on-chip antenna is doubled using helium-3 ion irradiation technique. The transmitter core is composed of a resistive-feedback RF amplifier, a double-balanced passive mixer, and an injection-locked oscillator. The wideband and power-saving design of the transmitter core guarantees the low-power and high-data-rate characteristic. The transmitter fabricated in a 65-nm CMOS process achieves 5-Gb/s data rate with an EVM performance of -12 dB for BPSK modulation at a distance of 1 mm. The whole transmitter consumes 17 mW from a 1.2-V supply and occupies a core area of 0.64 mm2 including the on-chip antenna. The gain-enhanced antenna together with the wideband and power-saving design of the transmitter provides a low-power low-cost full on-chip solution for the short-range high-data-rate wireless communication.
Negative feedback technique employing high DC gain operational amplifier (op-amp) is one of the most important techniques in analog circuit design. However, high DC gain op-amp is difficult to realize in scaled technology due to a decrease of intrinsic gain. In this paper, high DC gain op-amp using common-gate topology with high power efficiency is proposed. To achieve high DC gain, large output impedance is required but input transistors' drain conductance decreases output impedance of conventional topology such as folded cascode topology with complementary input. This is because bias current of the output side transistors is not separated from the bias current of the input transistors. On the other hand, proposed circuit can suppress a degradation of output impedance by inserting common-gate topology between input and output side. This architecture separates bias current of the input transistors from that of the output side, and hence the effect of the drain conductance of input transistors is reduced. As the result, proposed circuit can increase DC gain about 10 dB compared with the folded cascode topology with complementary input in 65 nm CMOS process. Moreover, power consumption can be reduced because input NMOS and PMOS share bias current. According to the simulation results, for the same power consumption, in the proposed circuit gain-bandwidth product (GBW) is improved by approximately 30% and noise is also reduced in comparison to the conventional topology.
This paper presents an inductive coupling interface using a relay transmission scheme and a low-skew 3D clock distribution network synchronized with an external reference clock source for 3D chip stacking. A relayed transmission scheme using one coil is proposed to reduce the number of coils in a data link. Coupled resonation is utilized for clock and data recovery (CDR) for the first time in the world, resulting in the elimination of a source-synchronous clock link. As a result, the total number of coils required is reduced to one-fifth of the conventional number required, yielding a significant improvement in data rate, layout area, and energy consumption. A low-skew 3D clock distribution network utilizes vertically coupled LC oscillators and horizontally coupled ring oscillators. The proposed frequency-locking and phase-pulling scheme widens the lock range to ± 10%. Two test chips were designed and fabricated in 0.18 μm CMOS. The bandwidth of the proposed interface using relay transmission ThruChip Interface (TCI) is 2.7 Gb/s/mm2; energy consumption per chip is 0.9 pJ/b/chip. Clock skew is less than 18- and 25- ps under a 1.8- and 0.9- V supply. The distributed RMS jitter is smaller than 1.72 ps.
This paper presents a novel architecture for a fault-tolerant and dual modular redundancy (DMR) system using a checkpoint recovery approach. The architecture features exploitation of SRAM with simultaneous copy and instantaneous compare function. It can perform low-latency data copying between dual cores. Therefore, it can carry out fast backup and rollback. Furthermore, it can reduce the power consumption during data comparison process compared to the cyclic redundancy check (CRC). Evaluation results show that, compared with the conventional checkpoint/restart DMR, the proposed architecture reduces the cycle overhead by 97.8% and achieves a 3.28% low-latency execution cycle even if a one-time fault occurs when executing the task. The proposed architecture provides high reliability for systems with a real-time requirement.
Monopulse is a classical technique for radar angle estimation and still adopted for fast angle estimation in phased array antenna. The classical formula can be applied to a 2-dimentional phased array antenna if two conditions—the unbiasedness and the independence of the azimuth and the elevation estimate—are satisfied. However, if the sum and difference beams are adapted to suppress the interference under jamming condition, they can be severely distorted. Thus the difference beams become highly correlated and violate the conditions. In this paper, we show the numerical implementation of the generalized monopulse estimation using the distorted and correlated beams, especially for a subarray configured antenna. Because we use the data from the measured subarray patterns rather than the mathematical model, this numerical method can be easily implemented for the complex array configuration and gives good performance for the uncertainty of the real system.
A primary-side regulation AC–DC constant voltage control chip is designed, which employs a novel cable compensation technique to improve the precision of the output voltage and pursue a wider load range for regulation. In the proposed controller, constant voltage (CV) is achieved by OSC charging current and current-limiting point adjustment. Meantime, according to different cable lengths, the sampled voltage is regulated by injecting current to pull-down resistance of the system to obtain an accurate output voltage. The proposed chip is implemented in TSMC 0.35 μm 5 V/40 V BCD process, and a 12 V/1 A circuit prototype has been built to verify the proposed control method. Experimental results show that the maximum cable compensation current reaches 43 μA, and the precision of the output voltage is within ± 3% in a wide range of output current from 0 to 1 A.
It is important to reduce the power consumption of complementary metal oxide semiconductor (CMOS) logic circuits, especially those used in mobile devices. A CMOS logic circuit consists of metal-oxide-semiconductor field-effect transistors (MOSFETs), which consume electrical power dynamically when they charge and discharge load capacitance that is connected to their output. Load capacitance mainly exists in wiring or buses, and transitions between logic 0 and logic 1 cause these charges and discharges. Many methods have been proposed to reduce these transitions. One novel method (called segmentation coding) has recently been proposed that reduces power consumption of CMOS buses carrying band-limited signals, such as audio data. It improves performance by employing dedicated encoders for the upper and lower bits of transmitted data, in which the transition characteristics of band-limited signals are utilized. However, it uses a conventional majority voting circuit in the encoder for lower bits, and the circuit uses many adders to count the number of 1s to calculate the Hamming distance between the transmitted data. This paper proposes segmentation coding with pseudo-majority voting. The proposed pseudo-majority voting circuit counts the number of 1s with fewer circuit resources than the conventional circuit by further utilizing the transition characteristics of band-limited signals. The effectiveness of the proposed method was demonstrated through computer simulations and experiments.
This paper presents the electrical contact behaviors of Au-plated material at super low making and breaking velocity conditions by introducing our new designed test rig. The fundamental phenomena in the contact voltage and contact force versus piezoactuator displacement curves were investigated under the load current of 1A and velocity of 50 nm/s. From the repetitive experimental results, we found that the adhesion phenomena during the unloading process are closely correlative with the initial contact stage in the loading process. Furthermore, a mathematical model which is relative to the variation of contact force in loading is built, thus the physical mechanism of adhesion and principal factors of gold-plated materials are discussed. Finally, the physical process of molten bridge under the no mechanical contact situation is also analyzed in detail.
The field electron emission characteristics of a p-type Si emitter sharpened by a spirally scanned Ga focused-ion-beam milling process were investigated. Saturated Fowler–Nordheim (F–N) plots, which are unique phenomena of p-type semiconductor emitters, were observed. The slight increase of the emission current in the saturated F–N plots region was discussed in terms of the depletion layer width in which electron generation occurs. The temperature dependence of the field electron emission current was also discussed. The activation energy of carrier generation was determined to be 0.26 eV, ascribable to the surface states that accompany the defects introduced by the Ga ion beam. When the emitter was irradiated by a 650-nm-wavelength laser, the increase in the emission current, i.e., the photoexcited emission current, was observed in the saturated region of the F–N plots. The photoexcited emission current was proportional to the laser intensity.
A class-E power amplifier (PA) with novel dynamic biasing scheme is proposed to enhance power added efficiency (PAE) over a wide power range. A look-up table (LUT) adjusts input power and drain supply voltage simultaneously to keep switch mode condition of a power transistor and to optimize the PAE. Experimental results show that the class-E PA using the proposed scheme with harmonic suppression filter gives the PAE higher than 80% over 8.5 dB range with less than 40 dBc harmonic suppression.